Embodiments of the invention relate generally to integrated circuit testing techniques. More specifically, the disclosure relates to a system, method, and program product for prioritizing clock domains used in the testing of integrated circuits.
The growing complexity and proliferation of integrated circuit (IC) chips has increased the demand for quality, cost-effective testing of the circuitry in each chip. Testing can be performed with external equipment and/or self-test circuitry. In the case of an external testing device, testing software may be installed on the external device. One scheme for testing an IC chip is Automatic Test Pattern Generation (ATPG). In ATPG, an “ATPG tool” can generate several test patterns, which are each run on the IC chip or circuit being tested. Each test pattern can be designed to detect the presence of particular errors in addition to unexpected or random errors. The generated test patterns, when applied, cause the circuit to generate an output pattern which can indicate the presence of faults or errors, such as design problems and manufacturing defects.
Some defects in an IC chip, e.g., in-line resistance, high impedance shorts, and cross talk between different signals, can only be identified when the circuitry is running at the intended speed of operation. A testing technique which may be used with ATPG is an “At-Speed Structural Test,” (ASST) in which the frequencies of the generated test patterns match the operational frequency of the IC chip. In an ASST, a “fault model” of the circuit representing all possible faults (or errors) may be built in software. The software can allow a user to select various portions, each of which may include several clock domains, of a circuit under test and generate “stimulus patterns” for each section. The faults tested by the software are each “marked off” until reaching a desired percentage of faults. The generated patterns can be “committed” after the desired percentage is reached, and the generated test patterns can be added to a global list stored in memory.
The circuitry of an IC chip may include multiple “parent” and “child” logic sections designed to operate at different frequencies. Some logic sections may be tested serially (one after another) while other logic sections can be tested in parallel. In an ASST, the presence of “parent” and “child” logic can reduce the accuracy and/or increase costs because a simulated clock signal may be limited to one frequency during a single test experiment. As a result, various “parent” and “child” sections of an IC chip may be tested multiple times. In addition or alternatively, parent logic circuits may be “marked off” after being tested below its operating frequency, and thus not tested at the maximum speed. Thus, considerations for testing an IC chip include sequencing the various “portions” of the circuit under test to assure that individual faults are tested at their highest application frequency, and generating the minimum possible number of test patterns, to avoid testing certain portions of the IC chip more than once.